Simple as Possible Computer 1 (SAP1) Architecture

 SAP-1(Simple as Possible-1) Computer Architecture


The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by Albert Paul Malvino. The SAP-1 design contains the basic necessities for a functional Microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor works, interacts with memory and other parts of the system like input and output. The instruction set is very limited and is simple.

The features in SAP-1 computer are:

  • W bus – A single 8 bit bus for address and data transfer.
  • 16 Bytes memory (RAM)
  • Registers are accumulator and B-register each of 8 bits.
  • Program counter – initializes from 0000 to 1111 during program execution.
  • Memory Address Register (MAR) to store memory addresses.
  • Adder/ Subtracter for addition and subtraction instructions.
  • A Control Unit
  • A Simple Output.
  • 6 machine state reserved for each instruction
  • The instruction format of SAP-1 Computer is


The first four bits make the Opcode while the last four bits make the operand (address).

Program Counter:

The program/Instructions are stored at the beginning of the memory with the first instruction at binary address 0000, the second at 0001 and so on. The PC is a part of the control unit. Its job is to send to the memory address register, the address of the next instruction to be executed and fetched. The PC is reset to 0000 before each computer run

Input and MAR:

The memory address register (MAR) is latched with the address of the pc during a computer run. A bit later, the MAR applies this 4-bit address to the RAM, where a real read operation is performed. It has some switch registers which helps it to do so.


The RAM is a 16×8 static TTL (Transistor Transistor Logic) RAM. During a computer run, the RAM receives 4-bit addresses from the MAR and a READ operation is performed. In this way, the instruction or data word stored in the RAM is placed on the W-bus.

Instruction Register:

1) The instruction register is part of the control unit.
2) To fetch an instruction from the memory the computer does a memory read operation. This places the contents of the addressed memory location on the W-bus.
3) At the same time, the IR is set up for loading on the next positive clock edge.
4) The contents of the IR are split into two nibbles.
5) The upper nibble is a two state output that goes directly to the block labeled ‘Controller-sequencer’.
6) The lower nibble is a three state output that is read onto the W-bus when needed.


1) Before each computer run, (CLR’) signal is sent to the PC and CLR signal to the IR.
2) This resets the PC to 0000 and wipes out the last instruction in the IR.
3) A clock signal CLK is sent to all buffer registers, this synchronizes the operation of the computer.
4) The 12 bits that come out of the CS form a word controlling the rest of the computer. The 12 wires carrying the control word are called the control bus.
5) The control word has the format:


This word determines how the registers will react to the next positive CLK edge.


1) The accumulator is a buffer register that stores immediate answers during a computer run.
2) It has two output. The first one goes directly to the Adder-Subtracter.
3) The three state output goes to the W-bus when EA is high.


1) When SU is low, the sum out of the adder-subtracter is


2) When SU is high, the sum out of the adder-subtracter is


3) The adder-subtractor is asynchronous (unlocked); this means that its contents can change as soon as the input words change.

4) When EU is high, these contents appear on the W-bus.

B Register:

1) The B register is also a buffer register.
2) A low LB‘ and positive CLK edge load the word on the W-bus into the B-register.
3) The two state output of the B register drives the B- register.

Output Register:

1) At the end of a computer run, the accumulator contains the answer to the problem being solved.
2) At this point, we need to transfer the answer to the outside world. This is where the output register is used.
3) When EA is high, is low, the next positive clock edge loads the word of the accumulator into the output register.
4) The output register is often called an output port processed data can leave the computer through these register.

Output Port:

1) The binary display is a row of 8 LEDs.
2) Each LED connects to one flip-flop of the output port.
3) After we have transferred an answer from the accumulator to the output port, we can see the answer in binary form.


Instruction of SAP-1 is of 8 bit length


First 4 bits are Opcode and last 4 bits are Operand

Example: LDA 9H and its binary equivalent is 0000 1001





Write a program to compute 16+20+24-32 (decimal) and display result in SAP-1 computer


Instruction Cycle:

Fetch Cycle

  • T1 (Address State)
  • T2 (Increment State)
  • T3 (Memory State)

Execution Cycle

  • 3 step (T4, T5, T6), but the task of each steps depends on the instruction


The control unit is the key to a computer’s automatic operation. The CU generates the control words that fetch and execute each instruction. While each instruction is fetched and executed, the computer passes through different timing states (T states), periods during which register contents modify

Control Signal During Each T state

Control Signal During Each T state

Execution Cycle (LDA Instruction)

  • For LDA instruction, only T4 and T5 states that will be active
  • T4: memory address is sent from IR to MAR
  • T5: data from memory is fetched and send to ACC
  • T6: do nothing (No Op)

Execution Cycle (ADD and SUB Instruction)

  • For ADD instruction, T4, T5 and T6 states that will be active
  • T4: memory address is sent from IR to MAR
  • T5: data from memory is fetched and send to B register
  • T6: Addition/ Subtraction takes place using the values stored in accumulator and B register. Addition takes place in ALU if SU low, Subtraction takes place if SU is high. Calculated value is stored in ACC when EU is high through w-bus.

Execution Cycle (OUT Instruction)

  • For OUT instruction, only T4 state will be active
  • T4: EA and LO’ will be active so data stored in Accumulator is loaded into Output register and displayed in the output unit.

Execution Cycle (HLT Instruction)

There is no execution cycle for HLT Cycle. When IR sends 1111 to the controller, it halts computer by turning off the clock

Figure: Fetch Cycle of SAP-1 Computer during program Execution

Figure: Fetch Cycle of SAP-1 Computer during program Execution

Figure: Execution Cycle of LDA Instruction

Figure: Execution Cycle of LDA Instruction

Figure: Execution Cycle of ADD Instruction

Figure: Execution Cycle of ADD Instruction

Timing Diagrams

Figure: Fetch and LDA timing diagram

Figure: Fetch and LDA timing diagram


The Sap-1 Microprogram


The controller-sequence sends out control words, one during each T- state or clock cycle. These words are like directions telling the rest of the computer what to do. Because it produces a small step in the data processing, each control word is called a micro-instruction.


The instructions LDA, ADD, SUB are sometimes called macro-instructions. Each Sap-1 macro-instruction is made up of three micro-instructions (i.e. T4, T5 and T6 state).

Control Matrix

The LDA, ADD, SUB and OUT signals from the instruction decoder drive the control matrix, at the same time, the ring counter signals, T1 to T6, are driving the matrix. The matrix produces CON, a 12-bit micro-instruction that tells the rest of the computer what to do.

Figure: SAP -1 Micro-Program

Figure: SAP -1 Micro-Program


The control matrix is one way to generate the microinstructions needed for each execution cycle. With larger instruction sets, the control matrix becomes very complicated and requires hundreds or even thousands of gates. Microprogramming is the alternative. The basic idea is to store microinstructions in a ROM rather than produce them with a control matrix. This approach simplifies the problem of building a controller-sequencer.

Storing the Micro-Program

These microinstructions can be stored in control ROM with the fetch routine at addresses at 0H to 2H, the LDA routine at addresses 3H to 5H,the ADD routine at 6H to 8H. To access any routine, we need to supply the correct addresses. For instance, to get the ADD routine, we need to supply addresses 6H, 7H and 8H.To get the OUT routine, we supply addresses CH, DH, EH. Therefore, accessing any routine requires three steps:

  1. Knowing the starting address of the routine
  2. Stepping through the routine addresses
  3. Applying the addresses to the control ROM.

Address ROM

The address ROM contains the starting addresses. The starting address of the LDA routine is 0011; the starting address of the ADD routine is 0110 and so on. When the op-code bits I7I6I5I4 drive the address ROM, the starting address is generated. For instance, if the ADD instruction is being executed, I7I6I5I4 is 0001.This is the input to the address ROM, the output of the ROM is 0110.

Presettable Counter

When computer run begins, the counter output is 0000 during T1 state, 0001 during T2 state, and 0011 during T3 state. Every Fetch cycle is the same because 0000, 0001, and 0010 come out of the counter during states T1, T2 and T3The op code in the IR controls the execution cycle. If an ADD instruction has been fetched, the I7I6I5I4 bits are 0001. These opcode bits drive the address ROM, producing an output of 0110.This starting address is the input to the presettable counter. When T3 is high the negative clock edge loads 0110 into the presettable counter. The counter is now preset, and counting can resume at the starting address of the ADD routine. The counter output is 0110 during T4 state, 0111 during T5 state and 1000 during T6 state.


Figure: Address ROM

Figure: Address ROM

Figure: Control ROM

Figure: Control ROM

Control ROM

The control ROM stores the SAP-1 microinstructions .During the fetch cycle; it receives addresses 0000, 0001, 0010. Therefore its outputs are

5E3H       //0101 1110 0011

BE3H       //1011 1110 0011

263H       //0010 0110 0011

These control bits is sent to different components of computer during T1, T2 and T3 state respectively.


Figure: Micro-Programmed ROM of SAP-1

Figure: Micro-Programmed ROM of SAP-1

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